DDR2 SDRAM

Part No.	W9751G6IB
Datasheet	W9751G6IB.pdf
Description	The W9751G6IB is a 512M bits DDR2 SDRAM, and speed involving -25/25F/-3. Status: Mass Production
Features	Power Supply: VDD, VDDQ = 1.8 V±0.1 V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, and 6 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS and /DQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK and /CLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS Posted /CAS programmable additive latency supported to make command and data bus efficiency Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality Auto-precharge operation for read and write bursts Auto Refresh and Self Refresh modes Precharged Power Down and Active Power Down Write Data Mask Write Latency = Read Latency - 1 (WL = RL - 1) Interface: SSTL_18
Diagram	N/A
Package	Packaged in WBGA 84 Ball (10X12.5mm²), using Lead free materials with RoHS compliant
Other Files	N/A
Development Tools	N/A
Others	N/A