Graphics DRAM

Part No.	W641GG2JB
Datasheet	W641GG2JB.pdf
Description	The W641GG2JB is a 1G GDDR3 and speed involving -12/-14 status: Mass Production
Features	Density: 1Gbit Powersupply (VDD, VDDQ): 1.8V±0.1V Organization:1 Chip Select x 8 banks x 4Mwordsx 32 bits (1-CS mode) and 2 Chip Select x 8 banks x 2M words x 32 bits (2-CSmode) Eight internal banks per Chip Select for concurrent operation 4n prefetch architecture: 128bit perarray Read or Write access Double-datarate architecture:two data transfers perclock cycle Single ended interface for data,address and command Differentialclockinputs CLK,CLK# Commandsentered on each positive CLK edge Single ended Read strobe (RDQS) per byte,edge-aligned with Read data Single ended Write strobe (WDQS) per byte, center-aligned with Write data Write data mask (DM) function DLL alignsDQ and RDQS transitions with CLK clock edgesfor Reads Burst length (BL): 4 or 8 Sequentialburst type only Programmable CASlatency:7 to 14 Programmable Write latency: 3 to 7 Auto precharge option for each burst access Pseudoopendrain outputs with 40Wpulldown,40Wpullup ODT:nom. values of 60W,120Wor 240W Programmable terminationand driver strength offsets Refresh cycles: 8192cycles/32ms Auto-refresh and self-refresh modes ODT and outputdrive strength auto-calibration with external resistorZQ pin (240W) Programmable IO interfaceincludingonchip termination (ODT) tRAS lockoutsupport Vendor ID for device identification Mirror function with MF pin Boundary Scan function with SEN pin  tWR programmable for Writes with Auto-Precharge Calibrated output drive. Active termination support ShortRAS to CAS timing for Writes Operating case temperaturerange: Tcase = 0°Cto +85°C
Diagram	N/A
Package	136 Balls TFBGA, using Lead free materials with RoHS compliant
Other Files	N/A
Development Tools	N/A
Others	N/A

Contact us: GraphicsDRAM@winbond.com